The present invention relates to a bit line dummy core-cell and a method for producing a bit line dummy core-cell.
Basic operations of semiconductor memory devices such as static random access memories (SRAMs) are reading and writing of data. In a conventional two-dimensional memory architecture, a word line connects to the gates of memory cell transistors in a row of memory cells, and a bit line connects to the sources or drains of the memory cell transistors in a column of memory cells. The operation of reading data in a typical semiconductor memory device is controlled by a signal, referred to as a read enable signal.
Said read enable signal is generated and provided by a logic SRAM memory compiler. In advanced technologies the realization of logic SRAM memory compilers is strongly dependent on some key design techniques. One of these key implementations is the realization of the so called bit line dummy concept.
The bit line dummy concept involves a dummy bit line, used as a part of the self-timing block in a memory macro providing a self-timing signal. The logic SRAM compiler generates said read enable signal dependent on said self-timing signal. The purpose of the dummy bit line is to represent and emulate the worst case capacitance, resistance and re-catch of an active array bit line during read and write operation.
The dummy bit line core-cell should track and reflect the same properties and dependencies on process and technology as the array bit line. Therefore, it is mandatory, that the core-cell of the dummy bit line is in terms of design and layout as close as possible to the SRAM array core-cell.
FIG. 1 shows a schematic view of a conventional bit line dummy core-cell array comprising m bit line dummy core-cells, wherein m designates the number of rows of the memory cells.
In the following, without loss of any generality, only the first bit line dummy core-cell 1 is explained in detail. The bit line dummy core-cell 1 comprises a first inverter 2 and a second inverter 3. The first inverter 2 and the second inverter 3 are cross-coupled to form a bistable flip-flop. The first inverter 2 comprises a first PMOS transistor 4 and a first NMOS transistor 5 connected in series by means of a first internal storage node 6 between a high reference potential VDD and a low reference potential VSS in particular. The high reference potential VDD is a power supply potential and the low reference potential is a ground potential. The second inverter 3 comprises a second PMOS transistor 7 and a second NMOS transistor 8 connected in series by means of a second internal storage node 9 between the high reference potential VDD and the low reference potential VSS.
Further, a first access transistor 11 is coupled between a dummy bit line 10 and the first internal storage node 6. Furthermore, a second access transistor 12 is coupled between the second internal storage node 9 and a bit line complement 13.
The first internal storage node 6 connects the drain of the first PMOS transistor 4 and the source of the first NMOS transistor 5. The second internal storage node 9 connects the drain of the second PMOS transistor 7 and the source of the second NMOS transistor 8. The gate of the first access transistor 11 is connected to a first word line 14 and the gate of the second access transistor 12 is connected to a second word line 15. In particular, both word lines 14, 15 are biased with the low reference potential VSS. Further, also the dummy bit line complement 13 coupled to the second access transistor 12 is connected to the low reference potential VSS.
During the read operation of the memory macro comprising the plurality of memory cells, the discharge of the dummy bit line 10 triggers the read sensing circuitry as part of the logic SRAM compiler. This means, that the dummy bit line 10 needs to represent the worst case capacitance, resistance and leakage current of any memory core-cell configuration, which could occur along a bit line.
The leakage current criterion is of special importance for the tuning of the self-timing path of the dummy bit line connected to said m bit line dummy core-cells for high performance memories. During the read operation, the development of the differential signal on the bit line and bit line complement results from the read current of the accessed cell in relation to the sum of the leakage currents of the non-selected cells on the same bit line. The leakage of the non-selected cells reduces the differential signal available for sensing the content of the cell during the read operation. A longer time is needed to read sufficient signal amplitude. Because the time for signal development is defined by the self-timing circuitry based on the dummy bit line, which is implemented, a too fast discharge of the dummy bit line due to the leakage and thus, an insufficient signal amplitude of the read signal must be avoided.
To minimize the amount of leakage current flowing through the dummy bit line, all the corresponding bit line dummy core-cells must store a logic high level or a logic one value. Under these conditions, the subthreshold leakage current through the access transistor of the cells is reduced dramatically. For the timing of the memory this corresponds to the worst case situation and as a result, the optimal self timing signal can be provided.